1. Field of the Invention
The present invention relates to a digital signal processing system (hereinafter referred to as xe2x80x98DSP systemxe2x80x99), and particularly relates to an apparatus, which captures data from an expansion bus at a fixed rate and subsequently inputs the data to a DSP device. Wherein, the DSP device receives information at another rate asynchronous to the fixed rate of the expansion bus.
2. Description of the Related Art
Many computer peripherals, for example, video cards, audio cards or specific PCMCIA cards, are comprised of DSP devices. Generally, A DSP device is comprised of a central processing unit (CPU), and is programmable so that it may be used to control the readings and writings of data, which is transferred via a plurality of signal lines coupled to the DSP device. However, instead of managing data at an optional schedule, some kinds of DSP devices, such as the DSP of an audio card, are designed to capture (or send out) data at fixed rates. FIG. 1 shows the prior art about a traditional PC audio system. The system comprises a DSP unit 1, a three-step first-in-first-out register (hereinafter referred to as xe2x80x98FIFOxe2x80x99) 5, an expansion bus 2, a south bridge unit 3, and an interface unit 4. Wherein, the south bridge unit 3 (for example, the Intel AC-97 Controller) communicates with the main bus (not shown) of the PC through a north bridge unit (not shown), and the interface control unit 4 is provided as a communicating interface between the DSP unit 1 and the expansion bus 2 (for example, a bus of AC-Link standard). The DSP unit 1 transmits a DRQ (data requisition) signal to the interface control unit 4, whereby the data, which is transferred through the interface unit 4 according to the protocol between the above-mentioned south and north bridge units, is available to the DSP unit 1. However, the DSP unit 1 is asynchronous to the data flow transferred in the expansion bus 2. To solve the problem, the data is pre-stored into the FIFO register 5. Accordingly, the DSP unit 1 captures the data from the expansion bus 2 indirectly by reading the data stored in the FIFO register 5.
However, the prior art has the disadvantage that the FIFO register 5 occupies a lot of area. It is disadvantageous for the size reduction of the DSP system.
The data flow in the bus is transferred in packets. In fact, to realize a system that captures data at a fixed rate, the point is a proper arrangement for the data-acquisition interval of the DSP device. Wherein, the data-acquisition interval is a period of time, which is required for the DSP to completely receive a packet of the data. The data-acquisition interval of the DSP should be contained in a data valid interval of the packet of data. Therefore, a buffer, such as the FIFO register mentioned above, is not necessary.
Accordingly, the present invention provides a DSP system, capturing the data from a main bus via a bus operating at the clock speed of a first frequency, and sending the data to a DSP unit reading the data at the clock speed of a second frequency, the DSP system comprising: a bus control unit, which is adapted to transfer data from the main bus to the bus; a pulse wave generator, producing a pulse wave that is synchronous to the bus. The pulse wave is comprised of sequential time slots, wherein a part of the time slots are DRQ slots that respectively comprise a data requesting signal, and the other times slots are normal slots; and an interface unit, capturing the data from the bus control unit via the bus according to the data requesting signal, and transmitting the data to the DSP unit.
Wherein, the interface unit transmits the data to the DSP unit in data valid intervals, and the DSP unit receives the data in data reading intervals, wherein each of the data reading intervals is covered by one of the data valid intervals.
Wherein one of the data requesting signals starts substantially at a first instance; another one of the data requesting signals and one of the data valid intervals start substantially at a same second instance; and the second instance is delayed from the first instance with one period corresponding to the first frequency.
Wherein, one of the DRQ slots, which comprises a data requesting signal starting at the first instance, is set as a first slot. For the first frequency is a, and the second frequency is b, and a greater than b, for natural numbers x and n, as the condition a(nxe2x88x921)/b less than xxe2x89xa6an/bxe2x88x921 is satisfied, the xth time slot behind the first slot is a normal slot. Furthermore, as the condition an/bxe2x88x921 less than xxe2x89xa6an/b is satisfied, the xth time slot behind the first slot is a DRQ slot.
Wherein, the data requesting signal is a data requesting pulse. The bus is in the AC-link standard, and the first frequency is substantially 48 KHZ. Wherein, the bus control unit is an AC-97 Controller, which is a south bridge controller.
Furthermore, the second frequency is substantially 44.1 KHZ. Additionally, the second frequency may be substantially 22.05 KHZ, 11.025 KHZ, 32 KHZ, 16 KHZ, or 8 KHZ.